This invention relates to a semiconductor integrated circuit device and to a technique which will be particularly effective when utilized for defects of a logic portion of a gate array integrated circuit or the like having logic gate circuits and memories, for example.
A gate array integrated circuit device having a large number of logic gate circuits is known. A memory equipped with a logic function which includes random access memories formed as a macro-cell and a logic portion for executing predetermined logical calculation processing for the stored data of the memories is also known.
The memory equipped with the logic function is described, for example, in "Digest Of Technical Papers", ISSCC, dated Feb. 15, 1989, Session II, pp. 26-27.
In the conventional logic integrated circuit device such as the memory equipped with the logic function as described above, the logic portion comprising the combination of a plurality of logic gate circuits is not provided with a redundancy for defect relief. Therefore, if abnormality occurs in any of the logic gate circuits or connection lines, the logic integrated circuit device is rejected as being a defective product and the production yield of the logic integrated circuit device drops. This problem becomes even more severe as the scale of the logic integrated circuit device becomes significantly increased and particularly when memories that are equipped with the defect relief function are mounted to the logic integrated circuit device. That is, the effect of the defect relief function thereof is spoiled. The present inventors examined a system employing a majority logic function by multiplexing the logic portion itself, for example, in order to cope with this problem however, this system cannot be practically implemented when the scale of the logic portion is great and its construction is complicated.